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<div class="header">
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<a href="#pub-attribs">Data Fields</a>  </div>
  <div class="headertitle"><div class="title">DCB_Type Struct Reference</div></div>
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<p>Structure type to access the Debug Control Block Registers (DCB).  
 <a href="structDCB__Type.html#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="pub-attribs" name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:acdf02aeb2b7c1eb26a0cbb8b0d51d1d4"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structDCB__Type.html#acdf02aeb2b7c1eb26a0cbb8b0d51d1d4">DAUTHCTRL</a></td></tr>
<tr class="memdesc:acdf02aeb2b7c1eb26a0cbb8b0d51d1d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x014 (R/W) Debug Authentication Control Register (Armv8-M only)  <br /></td></tr>
<tr class="separator:acdf02aeb2b7c1eb26a0cbb8b0d51d1d4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a91568edfba4a40c3f90196b7cda6f0ab"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structDCB__Type.html#a91568edfba4a40c3f90196b7cda6f0ab">DCRDR</a></td></tr>
<tr class="memdesc:a91568edfba4a40c3f90196b7cda6f0ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x008 (R/W) Debug Core Register Data Register.  <br /></td></tr>
<tr class="separator:a91568edfba4a40c3f90196b7cda6f0ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:addab25d3439fda1a7eff9ef21a8c3686"><td class="memItemLeft" align="right" valign="top">__OM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structDCB__Type.html#addab25d3439fda1a7eff9ef21a8c3686">DCRSR</a></td></tr>
<tr class="memdesc:addab25d3439fda1a7eff9ef21a8c3686"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x004 ( /W) Debug Core Register Selector Register.  <br /></td></tr>
<tr class="separator:addab25d3439fda1a7eff9ef21a8c3686"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a63c69742b24aa1a7d335426811e6e9be"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structDCB__Type.html#a63c69742b24aa1a7d335426811e6e9be">DEMCR</a></td></tr>
<tr class="memdesc:a63c69742b24aa1a7d335426811e6e9be"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x00C (R/W) Debug Exception and Monitor Control Register.  <br /></td></tr>
<tr class="separator:a63c69742b24aa1a7d335426811e6e9be"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6ed4cd7471c9f3c437a5d2cbaccceda7"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structDCB__Type.html#a6ed4cd7471c9f3c437a5d2cbaccceda7">DHCSR</a></td></tr>
<tr class="memdesc:a6ed4cd7471c9f3c437a5d2cbaccceda7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x000 (R/W) Debug Halting Control and Status Register.  <br /></td></tr>
<tr class="separator:a6ed4cd7471c9f3c437a5d2cbaccceda7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab55b3a94d700bb1021a92a36e4381efb"><td class="memItemLeft" align="right" valign="top">__OM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structDCB__Type.html#ab55b3a94d700bb1021a92a36e4381efb">DSCEMCR</a></td></tr>
<tr class="memdesc:ab55b3a94d700bb1021a92a36e4381efb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register (Armv8.1-M only)  <br /></td></tr>
<tr class="separator:ab55b3a94d700bb1021a92a36e4381efb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1937b89622a7aa02eef8a182587aa657"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structDCB__Type.html#a1937b89622a7aa02eef8a182587aa657">DSCSR</a></td></tr>
<tr class="memdesc:a1937b89622a7aa02eef8a182587aa657"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x018 (R/W) Debug Security Control and Status Register (Armv8-M only)  <br /></td></tr>
<tr class="separator:a1937b89622a7aa02eef8a182587aa657"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><p>Structure type to access the Debug Control Block Registers (DCB). </p>
</div><h2 class="groupheader">Field Documentation</h2>
<a id="acdf02aeb2b7c1eb26a0cbb8b0d51d1d4" name="acdf02aeb2b7c1eb26a0cbb8b0d51d1d4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#acdf02aeb2b7c1eb26a0cbb8b0d51d1d4">&#9670;&#160;</a></span>DAUTHCTRL</h2>

<div class="memitem">
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          <td class="memname">__IOM uint32_t DCB_Type::DAUTHCTRL</td>
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</div><div class="memdoc">

<p>Offset: 0x014 (R/W) Debug Authentication Control Register (Armv8-M only) </p>

</div>
</div>
<a id="a91568edfba4a40c3f90196b7cda6f0ab" name="a91568edfba4a40c3f90196b7cda6f0ab"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a91568edfba4a40c3f90196b7cda6f0ab">&#9670;&#160;</a></span>DCRDR</h2>

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          <td class="memname">__IOM uint32_t DCB_Type::DCRDR</td>
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</div><div class="memdoc">

<p>Offset: 0x008 (R/W) Debug Core Register Data Register. </p>

</div>
</div>
<a id="addab25d3439fda1a7eff9ef21a8c3686" name="addab25d3439fda1a7eff9ef21a8c3686"></a>
<h2 class="memtitle"><span class="permalink"><a href="#addab25d3439fda1a7eff9ef21a8c3686">&#9670;&#160;</a></span>DCRSR</h2>

<div class="memitem">
<div class="memproto">
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          <td class="memname">__OM uint32_t DCB_Type::DCRSR</td>
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</div><div class="memdoc">

<p>Offset: 0x004 ( /W) Debug Core Register Selector Register. </p>

</div>
</div>
<a id="a63c69742b24aa1a7d335426811e6e9be" name="a63c69742b24aa1a7d335426811e6e9be"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a63c69742b24aa1a7d335426811e6e9be">&#9670;&#160;</a></span>DEMCR</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__IOM uint32_t DCB_Type::DEMCR</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Offset: 0x00C (R/W) Debug Exception and Monitor Control Register. </p>

</div>
</div>
<a id="a6ed4cd7471c9f3c437a5d2cbaccceda7" name="a6ed4cd7471c9f3c437a5d2cbaccceda7"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a6ed4cd7471c9f3c437a5d2cbaccceda7">&#9670;&#160;</a></span>DHCSR</h2>

<div class="memitem">
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        <tr>
          <td class="memname">__IOM uint32_t DCB_Type::DHCSR</td>
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</div><div class="memdoc">

<p>Offset: 0x000 (R/W) Debug Halting Control and Status Register. </p>

</div>
</div>
<a id="ab55b3a94d700bb1021a92a36e4381efb" name="ab55b3a94d700bb1021a92a36e4381efb"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ab55b3a94d700bb1021a92a36e4381efb">&#9670;&#160;</a></span>DSCEMCR</h2>

<div class="memitem">
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        <tr>
          <td class="memname">__OM uint32_t DCB_Type::DSCEMCR</td>
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</div><div class="memdoc">

<p>Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register (Armv8.1-M only) </p>

</div>
</div>
<a id="a1937b89622a7aa02eef8a182587aa657" name="a1937b89622a7aa02eef8a182587aa657"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a1937b89622a7aa02eef8a182587aa657">&#9670;&#160;</a></span>DSCSR</h2>

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          <td class="memname">__IOM uint32_t DCB_Type::DSCSR</td>
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</div><div class="memdoc">

<p>Offset: 0x018 (R/W) Debug Security Control and Status Register (Armv8-M only) </p>

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